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Fuzzy motion adaptive algorithm and its hardware implementation for video de-interlacing

机译:视频去隔行的模糊运动自适应算法及其硬件实现

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摘要

Interlacing techniques were introduced in the early analog TV transmission systems as an efficient mechanism capable of halving the video bandwidth. Currently, interlacing is also used by some modern digital TV transmission systems, however, there is a problem at the receiver side since the majority of modern display devices require a progressive scanning. De-interlacing algorithms convert an interlaced video signal into a progressive one by performing interpolation. To achieve good de-interlacing results, dynamical and local image features should be considered. The gradual adaptation of the de-interlacing technique as a function of the level of motion detected in each pixel is a powerful method that can be carried out by means of fuzzy inference. The starting point of our study is an algorithm that uses a fuzzy inference system to evaluate motion locally (FMA algorithm). Our approach is based on convolution techniques to process a fuzzy rulebase for motion-adaptive de-interlacing. Different strategies based on bi-dimensional convolution techniques are proposed. In particular, the algorithm called 'single convolution algorithm' introduces significant advantages: a more accurate measurement of the level of motion using a matrix of weights, and a unique fuzzification process after the global estimation, which reduces the computational cost. Different architectures for the hardware implementation of this algorithm are described in VHDL language. The physical realization is carried out on a RC100 Celoxica FPGA development board. © 2010 Elsevier B.V.
机译:在早期的模拟电视传输系统中,隔行扫描技术是一种能够将视频带宽减半的有效机制。当前,一些现代数字电视传输系统也使用隔行扫描,但是,由于大多数现代显示设备都需要逐行扫描,因此在接收机端存在问题。去隔行算法通过执行插值将隔行视频信号转换为逐行视频信号。为了获得良好的去隔行效果,应考虑动态和局部图像特征。去隔行技术根据每个像素中检测到的运动水平而逐渐适应是一种强大的方法,可以通过模糊推理来实现。我们研究的出发点是使用模糊推理系统对运动进行局部评估的算法(FMA算法)。我们的方法基于卷积技术来处理用于运动自适应去交错的模糊规则库。提出了基于二维卷积技术的不同策略。特别地,称为“单卷积算法”的算法具有明显的优势:使用权重矩阵更精确地测量运动水平,以及在全局估计之后进行独特的模糊化过程,从而降低了计算成本。用VHDL语言描述了此算法的硬件实现的不同体系结构。物理实现是在RC100 Celoxica FPGA开发板上进行的。 ©2010 Elsevier B.V.

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